1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of forming an anode and a cathode of a substrate diode by performing angled ion implantation processes.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NMOS and PMOS transistors) represent one important type of circuit elements that substantially determine performance of the integrated circuits. A typical semiconductor chip will include millions of transistors and multiple levels of conductive interconnections to form the desired electrical circuits on the chip such that the chip may perform its intended operations.
One important issue, particularly in high performance devices, such as microprocessors and the like, is efficient management of the internal temperature of the integrated circuit device during operation. Depending upon the frequency and duration of use of an integrated circuit device, the internal temperature can rise due to the heat generated by the operation of the circuits and the transistors on the device. If the internal temperature of the chip is not monitored and maintained within acceptable limits, the operating performance of the device may be impaired or, in a worst case scenario, the integrated circuit device may be destroyed. Heat management is even more problematic for integrated circuit devices that are formed on silicon-on-insulator (SOI) substrates. An SOI substrate includes a bulk silicon substrate, a buried insulation layer (BOX) and an active layer, wherein the BOX layer is positioned between the bulk substrate and the active layer. Semiconductor devices are formed in and above the active layer. The use of the SOI substrates is beneficial for the electrical performance characteristics of devices formed on such an SOI substrate because the combination of the BOX layer (which is typically made of silicon dioxide) and surrounding trench isolation structure completely isolates the semiconductor device formed within the trench isolation structure and above the BOX layer. However, the presence of the BOX layer does reduce the heat dissipation capability of SOI devices as compared to device formed on a bulk silicon substrate. Thus, monitoring and sensing the temperature in SOI devices is of particular importance.
Typically, for thermal sensing applications, an appropriate substrate diode structure may be used wherein the electrical characteristics of the diode may be monitored to obtain regarding the thermal conditions in the vicinity of the diode structure. The sensitivity and the accuracy of the respective measurement data obtained from monitoring the substrate diode structure may depend significantly on the diode's characteristics, i.e., on the diode's current/voltage characteristic, which may depend on temperature and other parameters. In SOI devices, a corresponding substrate diode structure, i.e., the respective PN junction, is typically formed in the substrate material located below the buried insulating layer, above which is formed the “active” semiconductor layer used for forming therein the transistor elements.
FIGS. 1A-1B depict one illustrative example of a prior art substrate diode structure formed for an integrated circuit device 100. As shown therein, the substrate diode structure 101 is formed on a substrate 10 that is comprised of an active layer 10A, a buried insulation layer (BOX) 10B and a bulk silicon layer 10C. The substrate diode structure 101 generally comprises a cathode 30 and an anode 40. Also depicted in FIGS. 1A-1B is an illustrative transistor 20 comprised of a gate insulation layer 20A, a gate electrode 20B, sidewall spacers 16 and source/drain regions 22 formed in and above the active layer 10A of the substrate 10. An illustrative trench isolation structure 14 is provided to electrically isolate the transistor 20. The substrate diode structure 101 also includes an N-doped well 28 formed in the bulk silicon layer 10C, and N+ doped region 32 and a P+ doped region 42 formed within the N-doped well 28. At the point of fabrication depicted in FIGS. 1A-1B, the trenches 31, 41 have been formed for the cathode 30 and anode 40, respectively. The trenched 31, 41 extend through the active layer 10A and the BOX layer 10B. The trenches 31, 41 typically have the same configuration. In the example depicted in FIG. 1A, the trenches 31, 41 have a substantially square configuration, e.g., the dimensions 33, 43 and 45 are all about 500 nm.
A typical process flow for forming the substrate diode structure 101 will now be described. Typically, the N-doped well 28 is formed in the bulk silicon layer 10C prior to forming the trenches 31, 41 by performing a vertically-oriented ion implantation process with an N-type dopant through an implant mask (not shown), e.g., a photoresist mask, that locates the N-doped well 28 in the region of the device 100 where the cathode 30 and the anode 40 will be formed. Thereafter, the implant mask is stripped and a etch mask (not shown) is formed above the device 100 wherein the etch mask is patterned for the formation of the trenches 31, 41. One or more etching processes are then performed to form the trenched 31, 41. The etch mask is removed and first implant mask (not shown) is formed that covers the device 100 but exposes the trench 31. Then, a first vertically-oriented ion implantation process is performed with an N-type dopant to form the N+ doped region 32 within the N-doped well 28. The first implant mask is removed and a second implant mask (not shown) is formed that covers the device 100 but exposes the trench 41. Then, a second vertically-oriented ion implantation process is performed with a P-type dopant to form the P+ doped region 42 within the N-doped well 28. Thereafter, although not depicted in the drawings, metal silicide regions are formed on the N+ doped region 32 and the P+ doped region 42, and metal contacts are formed in the trenches 31, 41. In prior generation devices, the implantation processes performed to form the N+ doped region 32 and the P+ doped region 42 was part of the so-called deep source/drain implant processes performed to form the source/drain regions 22 on the transistor 20. However, in more recent generation devices, the desired dopant concentration of the N+ doped region 32 and the P+ doped region 42 is greater than can be obtained by combining such implant processes with the deep source/drain implant processes. Thus, separate ion implantation processes are typically now performed to form the N+ doped region 32 and the P+ doped region 42, as described above.
The present disclosure is directed to various novel methods of forming an anode and a cathode of a substrate diode.